Prime Finder Programmer's Guide.


Memory map:

FFFF FFFF	Program counter (PC)
FFFF FFFE	Prime test control register
FFFF FFFD	Prime test register
FFFF FFFC	LEDs/Switches (Lower half)
FFFF FFFB	ALU control and status register
FFFF FFFA	ALU a input
FFFF FFF9	ALU b input
FFFF FFF8	ALU output
FFFF FFF7	Zero
~~~~~~~~~	Reserved
0000 00FF	Memory top
~~~~~~~~~	Memory
0000 0000	Memory bottom


Notes on the processor:

The processor is a one instruction set processor (OISP). The only instruction that the processor executes is equivalent to mov (d),(s). The processor reads the memory location pointed to by 's', and then stores the data read from that location in the memory address pointed to by 'd'. To branch, the processor loads a word directly into the PC, which is located at the address FFFF_FFFF. Conditional branching is achieved by using the ALU to select between two or more different addresses to branch to. This functionality is built into the ALU to avoid the necessity for self-modifying code.


ALU Documentation:

The ALU has 4 registers that start at memory location FFFF_FFF8 and continue to FFFF_FFFFB.

Registers:

FFFF FFFB	ALU control and status register
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		C	S	V	P																								Function[3:0]
	C = Carry flag. C is set when the current operation results in a carry.
	S = Sign flag. S is set when the current operation results in a negative (2s-comp) number.
	V = Overflow flag. V is set when the current operation does not result in a carry and a negative number, or the current operation results in a carry and a positive number. V also equals C exor S.
	P = Parity flag. P is set when the current operation results in an odd parity.
	Function[3:0] is the function select. The functions are discussed later.
	
FFFF FFFA	ALU a input
	The 'a' ALU input.

FFFF FFF9	ALU a input
	The 'b' ALU input.
	
FFFF FFF8	ALU output
	The ALU output. Note that the current version of the ALU requires a write to this register before the result of the operation can be read. If a write is not performed, the result of the previous operation is read.
	
Functions:

The output of the ALU depends upon the value of Function[3:0].

0	a
1	b
2	a + b
3	a - b
4	a & b
5	a | b
6	a ^ b
7	carry*
8	a << 1
9	a >> 1
A	a < b*
B	a > b*
C	a <= b*
D	a >= b*
E	a == b*
F	a != b*

*These functions only apply the the rightmost bit. The other 31 bits are padded with zeros.


LEDs/Switches:

The 16 LEDs and switches are located in the right half of memory location FFFF_FFFC. The LEDs can only be written to and never read.


ZERO:

The ZERO register can only be read from. It is located at FFFF_FFF7 and has a constant output of 0000_0000.


Prime Testing Unit (PTU):

This piece of hardware uses repeated division to test whether a number is prime.

Registers:
FFFF FFFE	Prime test control register
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TF																													TE	TR	ST
	TF = Test Finished. TF is set when the input number has been fully tested.
	TE = Test Error. TE is set when a divide by zero occurs. Now that I think of it, this bit should never be set.
	TR = Test Result. TR is set if the input number is a prime.
	ST = Start Test. ST should be set to start the test. It is automatically cleared by hardware.
FFFF FFFD	Prime test register
	The number to be tested. The divider exhibits odd behavior when the MSB is set. It is recommended to only test 31-bit numbers as a result of this problem.


Program Counter:

The program counter is located at memory location FFFF_FFFF. It can be both read and written. No other methods of jumping are possible besides directly loading the PC.